System and method for using network interface card reset pin as indication of lock loss of a phase locked loop and brownout condition

ABSTRACT

A method for providing an indication from a network interface controller to a microcontroller is disclosed wherein upon occurrence of a particular condition within the network interface controller, an indication is provided from a reset pin of the network interface controller to the microcontroller unit. Upon receipt of the indication by the microcontroller unit, communications between the network interface controller and the microcontroller unit are inhibited.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. Pat. No. 7,325,167, entitledSYSTEM AND METHOD FOR USING NETWORK INTERFACE CARD RESET PIN ASINDICATION OF LOCK LOSS OF A PHASE LOCKED LOOP AND BROWNOUT CONDITIONissued on Jan. 29, 2008, incorporated herein by reference.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to network interface controllers, and moreparticularly, to a network interface controller using a reset pin toindicate lock loss of a phase locked loop and a brownout condition.

BACKGROUND OF THE INVENTION

Ethernet controllers have evolved from the original network card typesystems that provide network speeds of 2 Mb/s to 10 Mb/s, 100 Mb/s andup to current speeds of 1,000 Mb/s. The 2 Mb/s network interface cardshave all but disappeared. Most network interface systems, or networkinterface cards (NIC), currently provide for three higher speeds,10/100/1,0000 Mb/s. These are usually referred to as a 10 base T, 100base T, and 1,000 base T, the “T” referring to a twisted pair physicalmedia interface, other interfaces providing for the connection tooptical fibers and the like. Each of the various configurations, atwhatever speed, includes on an integrated circuit, a media side circuitor media access controller, the MAC, and a physical side circuit orphysical layer, the PHY. The NIC is operable to provide timing andencoding/decoding for receiving data and transmitting data. Typically,when data is transmitted over the physical transmission line, such as anRJ 45 twisted wire cable, data will be received by the NIC from aprocessing system and this data is stored in a FIFO of some sort,encoded for transmission and then transmitted. For received data, theopposite operation occurs. These are well known circuits and fairlycomplex. At higher speeds, the core processing circuitry basicallyrequires a digital signal processing (DSP) capability. Further, eachnetwork card will have associated therewith a unique address, such thatit is unique to all other address cards and can be disposed on anynetwork regardless of what other cards are disposed on the network. Thisis for the purpose of uniquely identifying any network device that isdisposed on the network apart from other network cards. To facilitatethis, a large block of numbers was originally created for the ethernetby a centralized standards body, which large block of numbers isconsidered to be an inexhaustible number.

The network interface cards further include an interrupt output and aninterrupt register for providing an indication of interrupt problemsbetween a network interface controller and an attached MCU. When aninterrupt condition occurs, this information related to the interruptcondition is stored within an interrupt register of the NIC card, and aninterrupt signal is sent from the NIC card to the attached MCU. Twoconditions which generate an interrupt from the NIC card to the attachedMCU are a loss of lock of the phase locked loop within the networkinterface card and the occurrence of a brownout condition within thenetwork interface card. Brownout occurs when the voltage of the networkinterface card drops below 3.1 V. While each of these conditions willcause an interrupt to be generated from the network interface card tothe attached MCU, during each of these conditions, the MCU is unable tocommunicate with the network interface card. Thus, while an interruptwill be received, there will be no way for the MCU to determine thecause of the interrupt, since the MCU will be unable to communicate withthe network interface card. Thus, some manner for providing anindication to an MCU from an attached network interface card that doesnot require the MCU to communicate with the interrupt register of thenetwork interface card is desired.

SUMMARY OF THE INVENTION

The present invention disclosed and claimed herein, in one aspectthereof, comprises a system and method for providing an indication froma network interface controller to a microcontroller unit. Upon detectionof a condition by the network interface controller, an indication isprovided from a reset pin of the network interface controller to themicrocontroller unit. Upon receipt of the indication by themicrocontroller unit, communications between the network interfacecontroller and the microcontroller unit are inhibited.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and theadvantages thereof, reference is now made to the following descriptiontaken in conjunction with the accompanying Drawings in which:

FIG. 1 illustrates a block diagram of a network controller interfacedwith a microcontroller that provides some functionality for interfacingwith peripherals and a network interface card;

FIG. 2 illustrates a block diagram of the network controller;

FIG. 3 illustrates a block diagram of the logic connected to the resetpin of the network interface card;

FIG. 4 is a flow diagram illustrating the operation of the networkinterface card responsive to a loss of phase lock of the phase lockedloop of the network interface card;

FIG. 5 is a flow diagram illustrating the operation of themicrocontroller unit responsive to loss of a phase lock in the phaselocked loop of the network interface card.

FIG. 6 is a flow diagram illustrating the operation of the networkinterface card during a brownout condition; and

FIG. 7 is a flow diagram illustrating the operation of themicrocontroller unit during a brownout condition.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is illustrated a diagrammatic view of anetwork appliance that is operable to be disposed on a network. Thenetwork appliance is basically interfaced to a network with some type ofphysical cable 102. In an Ethernet environment, this would be an RJ45cable. However, there could be other types of networks, even a wirelessnetwork. The physical cable is interfaced with a network interfacecontroller 104. This controller 104 has associated therewith a physicallayer section 106 that is labeled PHY. This provides for theencoding/decoding functions, the timing functions, etc., that arenecessary to interface with the network through the particular physicalmedia. For example, in an RJ45 cable, this is well known but differentthan for an optical cable, which would require a different set of timingrules, etc. The PHY 106 handles this encoding/decoding and timing. Onthe opposite side of the controller 104 is provided a media interfacedevice 108, referred to as a Media Access Controller (MAC). Thus, datacan be received on an input databus 110 from the media side, processedthrough the MAC 108 and the PHY 106 for transmission to the physicalcable 102. Conversely, data can be received from the physical cable 102,processed by the PHY 106 and MAC 108 and output on the databus 110.

The databus 110 is connected to a microcontroller 112, which is a devicethat provides minimal processing in this application. It has a digitalside to interface with the bus 110 and possibly some analog circuitry,such that the microcontroller 112 would constitute a mixed-signaldevice. Further, although not disclosed herein, the network controller104 could have a network address that was definable on an even largernetwork such as a global communication network (GCN) that is typicallyreferred to as the Internet.

Most Ethernet controllers will typically require some type of externalmemory to provide for storage of configuration information that will beloaded automatically at power-up. Typically, an EEPROM will be utilized,since it is both programmable and nonvolatile. The controller 104 hasbuilt therein non-volatile flash memory 112 that provides two functions.First, it provides for storage of configuration information on-chip.Second, as will be described in more detail herein below, it providesadditional external microcontroller memory to allow minimalfunctionality microcontrollers with little memory additional accessiblestorage space. Thus, the microcontroller 112, during the operationthereof, can access the flash memory 112 within the controller 104 forthe purpose of storing information thereof such as configurationinformation and such, and any other information necessary. Thisbasically takes a very unsophisticated microcontroller and providesadditional capabilities thereto.

The network interface controller 104 additionally includes a phaselocked loop (PLL) 114. The phase locked loop 114 enables thesynchronization of communications between the NIC 104 and themicrocontroller 112. The PLL 114 provides an out-of-lock signal when thephase locked loop 114 is out of phase lock. When the phase locked loop114 is out of phase lock communications between the microcontroller 112and network interface controller 104 are not possible.

An interrupt register 116 stores indications of interrupt conditionsthat occur within the network interface controller 104. When aninterrupt condition occurs, information describing the interruptcondition is stored within the interrupt register 116, and an interruptindication is provided from the network interface controller 104 to themicrocontroller 112 over an interrupt line 118. The microcontroller 112may then access the network interface controller 104 and the interruptregister 116 over the communications bus 110 in order to determine theinterrupt condition that has occurred. However, if the interruptcondition occurring within the network interface controller 104 iseither the loss of phase lock of the phase locked loop 114 or theoccurrence of a brownout condition where the voltage within the networkinterface controller 104 drops below 3.1 V, the network interfacecontroller 104 will be unable to communicate with the microcontroller112 over the communications bus 110. This will prevent themicrocontroller 112 from determining the interrupt condition storedwithin the interrupt register 116.

According to the present disclosure, the occurrence of loss of lock inthe phase locked loop 114 or a brownout condition will cause the networkinterface controller 104 to transmit an indication over the reset line120 interconnecting the network interface controller 104 andmicrocontroller 112. Normally the reset line 120 is a unidirectionalcommunication line wherein a reset signal is provided to the networkinterface controller 104 by the microcontroller 112 by pulling thesignal on the reset line 120 low. According to the present disclosure,the network interface controller 104 may provide an indication to themicrocontroller 112 of the occurrence of either a loss of lock by thephase locked loop 114 or the occurrence of a brownout condition bypulling the voltage on the reset line 120 low. If the microcontroller112 detects the voltage on the reset line 120 going low, it knows thatone of these two conditions has occurred. Thus, the reset line 120 isconfigured as a bi-directional line wherein a reset signal may beprovided from the microcontroller 112 to the network interfacecontroller 104, or an indication of the occurrence of a loss of lock bythe phase locked loop 114 or a brownout condition may be provided fromthe network interface controller 104 to the microcontroller 112.

Referring now to FIG. 2, there is illustrated a block diagram of thenetwork interface controller 104. This network interface controller 104is operable at the 10 Mb/s operating rate, such that it is a 10 BASE-Tdevice and can be completely realized on a single chip. In so doing, theentire network interface controller 104 can be fabricated on a singlechip with the on-chip flash. There is provided a databus 110 thatconstitutes the interface between the microcontroller 112 and thenetwork interface controller 102. There is provided in the networkinterface controller 102 a data interface to the databus 110 thatprovides for both multiplexed and non-multiplexed operations. For themultiplexed operation, there are provided eight address/data pins 202.For a non-multiplexed operation, there are provided eight additionaladdress pins 204. In the non-multiplexed operation, the pins 202 wouldbe data pins and the pins 204 would be address pins. This configurationfor interfacing with a databus utilizes the External Memory Interface(EMIF) format. This is a fairly standard interface that is utilized ondifferent manufacturers' parts, wherein each manufacturer may have aslightly different format. The EMIF interface is provided with a businterface block 206 that is operable to support one or two differentmanufacturers' EMIF memory interface formats, these being selected forconvenience purposes. Also, this will provide both multiplexed andnon-multiplexed formats. These formats are selected by two mode pins 208that allow for the selection between multiplexed and non-multiplexedoperation and also provides for two different interface formats. Onlyone mode pin is required for selecting between two different third partyformats. The bus bandwidth will provide sufficient throughput for the 10BASE-T throughput with a transaction speed that is less than 300ns/transaction. Reads and Writes to various memory locations andregisters are performed through using various EMIF command-addresses.For example, a Read from the location “RX_AUTO_INCREMENT” will perform aRead from the current receive buffer and will update a receive FIFOpointer. A Read or a Write from a “non-command” location will assume thelocation is a register that will provide the register Read value, i.e.,data, on the EMIF databus at the relevant time. There will be providedRead/Write commands on a pin 210, a chip select command on a pin 212 andother commands that are necessary. In general, any type of interfacecould be provided that would allow external access to memory on the chipby the microcontroller 112. There is provided the flash memory 112 thatis interfaced with the EMIF bus interface block 206. There is alsoprovided a Media Access Control (MAC) engine 220 that is fully compliantwith IEEE 802.3 Ethernet Standard (ISO/IEC 8802-3, 1993). This willbasically handle all aspects of the Ethernet frame, transmission andreception, including: collision detection, preamble generationdetection, and CRC generation and tests. There may even be includedvarious programmable features such as automatic re-transmission orcollision and automatic padding of transmitted frames. The MAC engine220 interfaces with the bus interface 206 through a bus 222. There willbe provided a MAC address nonvolatile RAM 224 that interfaces with theMAC engine 220 for the operation thereof. This provides configurationinformation to the MAC for the operation thereof. Although illustratedas a separate memory location, the MAC address RAM 224 is basically partof the nonvolatile flash 112, albeit in an address location dedicatedfor storage of configuration information. There are also provided a 2 KBtransmit RAM buffer 228 that is interfaced to the MAC engine 220 througha databus and a 4 KB receive RAM 230 that is interfaced to the MACengine 220 through the databus. Data that is being transmitted will bestored in the transmit RAM 228 and data that is being received will bestored in the receive RAM 230 during the operation thereof.

The MAC engine 220 interfaces with the PHY 106. The PHY 106 includes anencoder/decoder 236 that is operable to receive data from the MAC engine220 for encoding thereof and receive encoded data therefrom fortransmission to the bus 110. Encoded data for transmission is output toa transmit filter/driver block 238 for transmission on two transmitterminals 240 and 242. Data is received on two separate wires atterminals 244 and 246. This configuration is for a physical RJ45 cable,in this disclosed embodiment, such that there are two dedicated transmitpins and two dedicated receive pins. They will be interfaced through atransformer to a transmission line. The received data, once received, isprocessed through a receive filter/driver block 248 for decoding of thedata therein at the block 236. There is provided timing for the MACengine with an oscillator 250 that typically will require an externalcrystal on pins 252 and 254.

Most Ethernet controllers will require, as part of the IEEE standard,LEDs that Indicate that there is a link and an LED that indicates thatthere is activity. The link LED is connected to a pin 260 and theactivity LED is connected to a pin 262, both pins 260 and 262 controlledby an LED control block 264, which is controlled by the MAC engine 220.

The MAC engine 220 is also operable to generate an interrupt on a pin266 and receive a reset on pin 268. As such, the MAC engine will be ableto generate an interrupt to an external system that can utilize thisinterrupt to then access an interrupt register 270 for the purpose ofdetermining what interrupt occurred. This interrupt register 270represents two 8-bit registers.

In general, the receive interface is facilitated with the receive RAM230, which is basically a 4K FIFO that can support up to eight Readpackets. This 4K FIFO can be divided into a maximum of eight packetframes. The FIFO is written via hardware by the receive path of the MACengine 220, and is read by software via the EMIF interface 206. Thetransmit interface is facilitated with the transmit RAM 228 that is a 2Ksingle ported RAM buffer. This buffer will be written a byte at a timevia the EMIF bus interface block 206 with the packet that is to betransmitted. Once the entire packet has been placed in this RAM 228, a“BEGIN_TX” bit is set which then begins a transmit session to the MACengine 220. During transmission, a flag is set indicating that thetransmit engine is busy. Once the transmission is complete, this bitwill be cleared and an interrupt will be generated on the interrupt pin266 indicating that the transmission has been completed. The transmitengine will support features such as transmitting a pause packet,applying back pressure (half duplex) and overriding the CRC and paddingcapabilities on a per packet basis. The packet based-transmission oncollision, etc. is handled automatically with the MAC engine 220.Basically, transmission is facilitated by first writing the startaddress of the transmit packet (usually “x0000”) to an address register.This is followed by writing data to a TX_AUTO_INCREMENT registerlocation which will place the data in the location pointed to by theaddress register. Thereafter, transmission is initiated by writing thestart address to the address register and then writing a “1” to the“TX_start” bit in the transmit control register.

The flash 112 can be accessed via the EMIF bus interface 206 for Readsand Writes. There are provided some ADDRH/L registers that should firstbe written with the starting address. Thereafter, an auto-increment Readcan be performed or a single-byte Write (or Read) can be performed.Flash mass erases are typically not permitted by the user. These areprotected by a lock and key mechanism that will prevent a user fromdeleting information accidentally. Another lock and key mechanism alsoprotects Writes. Once unlocked, back-to-back Writes to the flash will bepossible. To unlock a Write operation, it is necessary to performback-to-back Write operations to a particular address with somepredefined data which is the “key.”

There are a number of flash interface registers that are contained inthe bus interface. There is a FLASHLOCK register that is operable toperform Writes or page/mass erases with the address values A5, F1, whichneed to be written to this location consecutively. There is provided anINFOPGWR register that allows the performance of mass erases. To performmass erases or to write to an information page, a code is required to bewritten consecutively to this location. There is provided a FLASH ERASEregister which can allow for initiating a page erase or a mass erase. AFLASH STATUS register provides status information as to if the flash ishaving a page erase performed, being mass erased, a flash Write isoccurring, the flash is busy or that the flash has been erased since thelast reset. There is an ADDRH/L register that is an address registerused to access the flash. To Read or Write flash, it is necessary tofirst write the address of the byte to be accessed in this location andthen perform the auto-increment operation for Reads or the 1-byteoperation for a Read or a Write, these being EMIF commands. With theauto-increment command, only the address of the first byte needs to bewritten, with subsequent Reads all incrementing this address.

A multiplexer 271 and phase locked loop 273 are connected between theMAC engine 220 and the oscillator 250. The multiplexer 271 comprises atwo to one multiplexer having its first input connected to an output ofthe phase locked loop 273 and its second input connected to an output ofthe oscillator 250. The output of the multiplexer 271 is connected to aninput of the MAC engine 220. The phase locked loop 273 has its outputconnected to the multiplexer 271 and its input connected to receive theclock signal from oscillator 250. Phase locked loop 273 multiplies upthe clock signal provided by the oscillator 250. A clock select signalselects between the output of the phase locked loop 273 and the outputof the oscillator 250 to provide a clock signal for the networkinterface controller. The phase locked loop 273 would also provide aloss of lock signal to indicate that the phase lock of the phase lockedloop 273 has been lost. This loss of lock signal is provided tocombinational logic 310 and may be used to provide an indication to themicrocontroller unit 112 on the reset line 120. The VDD monitor 277monitors the VDD voltage of the NIC 104. If the voltage falls below 3.1V, a brownout condition signal is generated by the VDD monitor 277 andprovided to the combinational logic 310. The VDD monitor also canprovide a brownout reset signal to the RST Funnel 279.

Referring now to FIG. 3, there is illustrated the connection of thedriver circuitry for the reset (RST-bar) pin 302. The reset pin 302 isconnected to the reset line 120. The reset line 120 is held activelyhigh by a pull up resistor 304. Reset pin 302 of the network interfacecontroller 104 is connected to an input line driver 306 throughcombinational logic 310 which is connected to the reset circuitry withinthe network interface controller 104. The reset pin 302 is alsoconnected through combinational logic 310 to an output driver 308 forproviding an output signal over the reset pin 302 to the reset line 120.The combinational logic is responsive to a lock detect signal from thephase locked loop and a brownout signal indicating the voltage of thenetwork interface card has dropped below 3.1 V. As described previously,the lock detect signal would come from the phase locked loop 114. Thebrownout signal would be provided by the VDD monitor 277. Thecombinational logic 310 is configured such that the signal provided tothe input of driver 308 and the input of driver 306 enable the resetline 120 to be pulled low by the network interface card 104 in responseto an indication of a brownout condition by the brownout signal or aloss of lock by the lock detect signal. While the reset line 120 ispulled low, the output of driver 306 remains high in order to preventthe occurrence of a reset cycle within the network interface controller104. Likewise, the combinational logic 310 enables the reset line 120 tobe pulled low by the attached MCU to initiate a reset cycle to beinitiated within the NIC 104. If a loss of phase lock or brown outoccurs then an interrupt is signaled externally and a reset is generatedinternal to the chip.

Referring now to FIG. 4, there is illustrated a flow diagram describingthe operation of the network interface card 104 wherein the reset pin isused to indicate a loss of lock in a phase locked loop 273. The processbegins at step 502. Inquiry step 504 determines if there is a lockdetect from the phase locked loop 273. If a lock exists, inquiry step504 continues to monitor for the lock detect of the phase locked loop273. If no lock detect is detected, the RST-bar pin is pulled low atstep 506. Inquiry step 510 monitors for the lock detect signal and whilethe phase locked loop 273 remains out of lock, inquiry step 510continues monitoring. Once inquiry step 510 detects that the phaselocked loop 114 has re-entered phase lock, an interrupt is generated atstep 512 to the microcontroller unit over interrupt line 118. Theprocess ends at step 514.

Referring now to FIG. 5, there is illustrated the operation of themicrocontroller unit 112 responsive to the indication received from thenetwork interface card 104 over the reset line 120. The process beginsat step 602 and inquiry step 604 monitors the reset line at step 604 todetermine if it has gone low. If not, inquiry step 604 continuesmonitoring until the reset line 120 goes low. Once the reset line goeslow, the microcontroller unit 112 knows that a loss of phase lock hasoccurred and inhibits communications, at step 606, between themicrocontroller unit 112 and the network interface controller 104.Inquiry step 608 begins monitoring for receipt of the interrupt signal118 from the network interface controller 104. The interrupt signalprovides an indication that the loss of lock condition has ended, thusenabling resumption of communications between the network interfacecontroller 104 and the microcontroller 112. Inquiry step 608 continuesmonitoring if no interrupt signal is detected. Once the interrupt signalis detected by inquiry step 608, communications resume at step 610between the microcontroller 112 and the network's interface card 104.The process returns to normal operation at step 612.

Referring now to FIG. 6, there is illustrated a flow diagram describingthe operation of the network interface card 104 wherein the reset pin isused to indicate a brownout condition. The process begins at step 702.Inquiry step 704 determines if there is a brownout condition. If nobrownout condition exists, inquiry step 704 continues to monitor forbrownout. If a brownout condition is detected, the RST-bar line ispulled low at step 706. Inquiry step 710 monitors the brownout conditionand while the brownout condition remains, inquiry step 710 continuesmonitoring. Once inquiry step 710 detects that brownout has ended, aninterrupt is generated at step 712 to the microcontroller unit overinterrupt line 118. The process ends at step 714.

Referring now to FIG. 7, there is illustrated the operation of themicrocontroller unit 112 responsive to the brownout indication receivedfrom the network interface card 104 over the reset line 120. The processbegins at step 802 and inquiry step 804 monitors the reset line at step804 to determine if it has gone low. If not, inquiry step 804 continuesmonitoring until the reset line 120 goes low. Once the reset line goeslow, the microcontroller unit 112 knows that a brownout condition hasoccurred and inhibits communications, at step 806, between themicrocontroller unit 112 and the network interface controller 104.Inquiry step 808 begins monitoring for receipt of the interrupt signal118 from the network interface controller 104. The interrupt signalprovides an indication that the brownout condition has ended, thusenabling resumption of communications between the network interfacecontroller 104 and the microcontroller 112. Inquiry step 808 continuesmonitoring if no interrupt signal is detected. Once the interrupt signalis detected by inquiry step 808, communications resume at step 810between the microcontroller 112 and the network's interface card 104.The process returns to normal operation at step 812.

Although the preferred embodiment has been described in detail, itshould be understood that various changes, substitutions and alterationscan be made therein without departing from the scope of the invention asdefined by the appended claims.

1. A method for providing an indication from a network interfacecontroller of a condition that will cause the network interfacecontroller to be reset and will prevent communication between thenetwork interface controller and external circuitry, comprising thesteps of: detecting occurrence of a condition in the network interfacecontroller that would cause the network interface controller to be resetand which will substantially prevent communication between the networkinterface controller and the external circuitry; providing theindication from a reset pin of the network interface controller afterdetection of occurrence of the condition while, at substantially thesame time, internally generating an internal reset to the networkinterface controller; and inhibiting attempts at communication betweenthe network interface controller and the external circuitry by theexternal circuitry responsive to the step of providing the indicationvia initiation of the reset in the network interface controller.
 2. Themethod of claim 1, wherein the condition comprises a lock loss for aphase locked loop.
 3. The method of claim 1, wherein the conditioncomprises a brownout condition of the network interface controller. 4.The method of claim 1, wherein the step of providing further comprisesthe step of pulling a reset line connected to the reset pin from a firstvoltage level to a second voltage level.
 5. The method of claim 1,further including the steps of: detecting occurrence of a secondcondition in the network interface controller; and providing aninterrupt from the network interface controller to the microcontrollerunit after detection of occurrence of the second condition.
 6. Themethod of claim 5, wherein the second condition comprises a phase lockfor a phase locked loop.
 7. The method of claim 5, wherein the secondcondition comprises a non-brownout condition of the network interfacecontroller.
 8. A network interface controller for interfacing between aphysical network and a media, comprising: a physical layer for receivingdata for encoding and transmission to the physical network, and forreceiving data from the physical network and decoding the received data;a media layer for receiving data from a microcontroller unit andconverting the received data to a packet format and interfacing withsaid physical layer for transmitting packet formatted data thereto forencoding and transmission thereof, and for receiving decoded packetformatted data from said physical layer; a phase locked loop enablingsynchronization of communication between the network interfacecontroller and the microcontroller unit, said phase locked loopgenerating a signal indicating loss of phase lock; a reset pin providinga bidirectional interface between the network interface controller andthe microcontroller unit; and combinational logic for providing anindication from the reset pin of the network interface controllerresponsive to the signal from the phase locked loop that the phaselocked loop is operating in a mode that will prevent communicationbetween the network interface controller and the microcontroller unit,and for providing at substantially the same time an internal resetsignal to the network interface controller, wherein the indicationprovided via initiation of a reset in the network interface controllerinhibits attempts at communication by the microcontroller unit betweenthe network interface controller and the microcontroller unit.
 9. Thenetwork interface controller of claim 8, wherein the combinational logicfurther pulls a reset line connected to the reset pin from a firstvoltage level to a second voltage level.
 10. The network interfacecontroller of claim 8, further includes circuitry for detectingoccurrence of a second condition in the network interface controller,and providing an interrupt from the network interface controller to themicrocontroller unit after detection of occurrence of the secondcondition.
 11. The network interface controller of claim 10, wherein thesecond condition comprises a phase lock for a phase locked loop.
 12. Thenetwork interface controller of claim 8, further including a VDD monitorfor monitoring a VDD voltage of the network interface controller and forgenerating a brownout signal when the VDD voltage falls below a firstlevel.
 13. The network interface controller of claim 12, wherein thecombinational logic further provides the indication from the reset pinof the network interface controller responsive to the brownout signal.14. The network interface controller of claim 13, further includescircuitry for detecting occurrence of a second condition in the networkinterface controller, and providing an interrupt from the networkinterface controller to the microcontroller unit after detection ofoccurrence of the second condition.
 15. The network interface controllerof claim 14, wherein the second condition comprises a non-brownoutcondition.